The present invention relates generally to electronic integrated circuit wiring techniques. More particularly, the present invention relates to on-chip interconnect circuits with use of large-sized copper fill in CMP processing.
In the -chemical mechanical polishing (CMP) process of dual damascene copper back-end-of-line (BEOL), minimum copper densities must be present over the local areas of the wafer to maintain planarity during polishing. Correct copper densities are achieved in low-density areas by adding dummy copper shapes in the circuit design; these dummy shapes are known as fill. Process engineers have identified that fill shapes larger than the minimum linewidth improve manufacturing yield. However, little attention has been paid to the fill impact on electrical performance of interconnect circuits, other than a relatively larger effective capacitance of the dielectric stack. At high frequencies, the AC coupling between the interconnect signals and fill shapes can be significant and excessive capacitance can reduce circuit performance.
High frequency interconnect circuits consist of a signal line and an appropriate ground reference nearby. Such ground reference can be either a DC ground or an AC ground with a static reference potential other than 0 Volts. Characteristic impedance for interconnect circuits is accomplished by design of signal line width and separation to the reference ground conductors. The regions of white space (absence of metal) between the signal and ground or adjacent to a signal line without ground is therefore critical in control of the characteristic impedance and capacitance per unit length of the interconnect.
Sub-micron fill shapes at 10-50% area densities effectively increase the strength of electric fields in a pejorative way for copper interconnect circuits. The larger capacitance can be compensated in the design of the interconnect by proportionately increasing the inductance. However, this may either increase the conductor resistance or reduce the signal routing density, both of which are undesirable.
Accordingly, a need exists to lower the capacitance in high-frequency interconnect circuits that utilize copper fill shapes.
The invention is a design method to lower the capacitance in high-frequency interconnect circuits built using copper dual-damascene back-end-of-line (BEOL). The method achieves lower interconnect capacitance by reducing capacitance to parasitic copper fill shapes. Parasitic capacitance is reduced physically by a) stacking copper fill shapes on each copper layer, and b) using larger dimension fill shapes. The consequence of using larger dimension fill shapes is to: a) increase white space between fill shapes, and b) reduce the summed perimeter of the fill shapes.